It is of ultimate importance for portable or mobile electronic systems to have a battery life that sustains a reasonably long period of time, typically for hours but sometimes for days or even weeks, between a battery charging event and the next. For this purpose, contemporary CMOS ICs employed by such a portable system often resort to advanced power management schemes that include durations of operation called “partial power down” (PPD). During PPD, portions of the system (that is, some domains of the CMOS system) that are not in use, typically called “power down (PD) domains”, are powered down to reduce standby power consumption. The terms “CMOS IC” and “CMOS system” are used interchangeably herein.
When a domain of a CMOS IC is powered down during PPD, some devices in the PD domain may need to continue operating, or remain “on”, while other CMOS devices if the domain is powered down. These devices that remain “on” are called “always-on” (AON) cells. Typically, the AON cells operate from a supply voltage different from the supply voltage from which other CMOS cells that are powered down during PPD operate from. FIG. 12 is a schematic diagram of a portion 1200 of such a PD domain implemented in a conventional way. Specifically, the PD domain includes a regular CMOS cell 1210 that is configured to be powered down during PPD and a CMOS AON cell 1220 that is configured to remain operating during PPD. As shown in FIG. 12, CMOS cell 1210 has its p-type metal oxide semiconductor (PMOS) source terminal 1211 connected to a supply voltage “local VDD” that is configured to be disabled to the PD domain during PDD. On the other hand, CMOS cell 1220 has its PMOS source terminal 1221 connected to a supply voltage “global VDD” that is configured to stay on and available to the PD domain during PDD. Conventionally, a PMOS device of a CMOS cell is connected in a “local tie” configuration; that is, the body terminal of the PMOS device of the CMOS cell (i.e., the N-well terminal of the CMOS cell) is connected together with the source terminal of the PMOS device. Therefore, in a conventional implementation of a PD domain having an AON cell as shown in FIG. 12, CMOS cell 1210 has its NW terminal connected to the local VDD, whereas CMOS cell 1220 has its NW terminal connected to the global VDD.
The local VDD and the global VDD may have different voltage levels. Namely, the N-well (NW) of CMOS cell 1210 may be biased at a different voltage level than the NW of CMOS cell 1220. It is well known in the art that when two NWs biased at different voltage levels are manufactured on the same semiconductor substrate, the two NWs cannot be placed side-by-side and abutting with each other. Instead, certain NW-to-NW spacing is required between the two NWs so that they can be manufactured properly.
FIG. 13 illustrates a physical realization 1300 of the two CMOS cells in the schematic diagram of FIG. 12 may be physically realized on a semiconductor substrate. As can be seen in FIG. 13, each of the two CMOS cells has a respective NW, one biased to the local VDD and the other biased to the global VDD. Specifically, each of NW terminal 1351 and supply terminal 1361 of regular CMOS cell 1310 is connected to the local supply that is to be disabled during PPD, while each of NW terminal 1352 and supply terminal 1362 of AON CMOS cell 1320 is connected to the global supply that remains available during PPD. N-well 1342 of the AON cell is biased at the voltage level of global VDD through NW terminal 1352 for both normal operation periods and partial power down periods. On the other hand, N-well 1341 of the regular cell is biased at the voltage level of local VDD through NW terminal 1351 only during normal operation. Notably, the two NWs do not abut against each other, as the global VDD may be at a different voltage level than the local VDD. Instead, a NW-to-NW spacing 1380 is required between the two NWs.
To ensure a proper NW-to-NW spacing is presented between two separate N-wells, a NW-to-NW spacing design rule is typically imposed by a semiconductor manufacturer (the “foundry”). The design rule is necessary to guarantee the quality of the manufactured semiconductor chips. A foundry manufactures a semiconductor chip according to a database containing a physical description of the intended semiconductor circuitry. This database is presented by 2-dimensional (2D) layout design files describing how the semiconductor circuitry is intended to be physically made. The layout may include dimension and connection information of the CMOS cells forming the circuitry. Before the foundry actually start to transform the semiconductor design into a physical product, the foundry would use a set of so-called “design rules” to check the layout database of the design to make sure the physical design according to the layout database can be faithfully and satisfactorily realized via its manufacturing process. A checking of the NW-to-NW spacing is included in the design rules, and the physical layout has to pass the checking to ensure the required NW-to-NW spacing is not accidentally omitted.
Conventionally, on the design end, NW-to-NW spacing is included in an AON cell layout to ensure the design rule check (DRC) of the NW spacing is fulfilled. FIG. 14 is an illustration of a 2D layout 1400 of a conventional AON cell. As can be seen in FIG. 14, NW spacing 1420 and NW spacing 1430 (that is, unutilized silicon areas containing no N-well) are included in the layout on both the left and right sides of the layout. Therefore, when put together with other CMOS cells of a PD domain, NW-to-NW spacing is naturally guaranteed between separate N-wells 1510, 1520, 1530, 1540, 1550 and 1560 in the overall 2D layout of the PD domain, such as the 2D layout 1550 of a MV CMOS IC shown in FIG. 15. 2D layout 1400 of the conventional AON cell also includes at least one always-on tap (ATAP) 1440 that is disposed in NW 1410 and configured to be connected to global supply so as to bias NW 1410 to the voltage level of global VDD. In addition, local VDD metal stripe 1450 and ground (VSS) metal stripe 1460 are also included in 2D layout 1400 of the conventional AON cell so as to facilitate abutment against adjacent CMOS cells, even though local VDD metal stripe 1450 is not electrically part of the conventional AON cell.
As CMOS manufacturing technologies evolve and improve from generation to generation, physical sizes of CMOS transistors and cells, or “gates”, are greatly reduced. The technology improvement gives rise to highly integrated CMOS ICs and systems that pack millions or even trillions of gates on a small piece of semiconductor substrate. Unfortunately, however, the required NW-to-NW spacing does not scale down at the same rate as the CMOS devices. As a result, a higher and higher percentage of precious substrate real estate is occupied by the required NW-to-NW spacing around the AON cells. The NW-to-NW spacing do not actively contribute to the functionalities of the CMOS system, and thus are considered an overhead of the system. Take the AON cell of FIG. 15 as an example, the AON cell layout may be 3.78 μm in total width, representing a buffer cell in a 28 nm process. The NW spacing on both the left and right side of the cell of FIG. 15 may collectively take up 45% of the cell width, which translates to 45% of the cell area. In view of FIG. 15 where AON cells and regular cells are put together, significant silicon area is also taken by the NW spacing around the AON cells.